The present invention relates to an integrated circuit device such as a digital signal processor which is required fast processing of an internal signal.
For example, a digital audio system is comprised of a plurality of large scale integrated circuit devices (LSIs) which utilize a common clock signal for executing certain signal processings. The typical LSI fabricated by current LSI production technology has an operating speed up to 20 MHz-50 MHz. In near future, the operating speed is expected to reach an order of several hundreds MHz. Therefore, the audio system may need a fast clock signal for internal data processing by the LSI, which is far faster than a data sampling frequency of, for example, 44.1 kHz adopted by the audio system.
Generally, a quartz crystal oscillator is utilized as an external clock source for the LSI. The quartz crystal oscillator may generate a clock signal having a frequency up to 100 MHz in practical level. However, common use of such a fast clock signal among plural LSIs may cause various drawbacks. First, it may be practically difficult to transfer such a fast clock signal along a circuit board which supports the plural LSIs. Second, it may be practically difficult to admit the fast clock signal inside the LSI even though the fast clock signal is delivered to a clock input terminal of the LSI. Third, it may be difficult to maintain constantly the phase relation between a system clock signal and an internal clock signal of each LSI.